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UTB 36 - Part-2: ASIC Physical Design and Verification of I2C(Inter-Integrated Circuit) Protocol using Cadence EDA Tools (Netlist-to-GDSII) cover

UTB 36 - Part-2: ASIC Physical Design and Verification of I2C(Inter-Integrated Circuit) Protocol using Cadence EDA Tools (Netlist-to-GDSII)

Navaneetha Krishnan

UTB36 - Part-1: ASIC Design and Verification of I2C(Inter-Integrated Circuit) Protocol using Cadence EDA Tools (RTL-to-Netlist) cover

UTB36 - Part-1: ASIC Design and Verification of I2C(Inter-Integrated Circuit) Protocol using Cadence EDA Tools (RTL-to-Netlist)

Ashwini H, Pooja C

Mech UTB06 - Demonstration of Single cylinder crankshaft using CAD Tool cover

Mech UTB06 - Demonstration of Single cylinder crankshaft using CAD Tool

Vinayak S T

UTB35 - Part-2: ASIC Physical Design and Verification of FIFO using Cadence EDA Tools (Netlist-to-GDSII) cover

UTB35 - Part-2: ASIC Physical Design and Verification of FIFO using Cadence EDA Tools (Netlist-to-GDSII)

Navaneetha Krishnan, Pooja C

Mech UTB05 - Demonstration of Flang e Coupling Assembly using CAD Tool cover

Mech UTB05 - Demonstration of Flang e Coupling Assembly using CAD Tool

Vinod M I

Mech UTB04 - Demonstration of Piston Head & Connecting Rod Assembly using CAD Tool cover

Mech UTB04 - Demonstration of Piston Head & Connecting Rod Assembly using CAD Tool

Vinod M I

Mech UTB02 - Demonstration of a Plummer Block using a CAD Tool cover

Mech UTB02 - Demonstration of a Plummer Block using a CAD Tool

Gokul Raj M

UTB35 - Part-1: ASIC Design and Verification of FIFO (First In-First Out) using Cadence EDA Tools (RTL-to-Netlist) cover

UTB35 - Part-1: ASIC Design and Verification of FIFO (First In-First Out) using Cadence EDA Tools (RTL-to-Netlist)

Ashwini H, Pooja C

Mech UTB01 - Introduction to Computer Aided Design (CAD) cover

Mech UTB01 - Introduction to Computer Aided Design (CAD)

Gokul Raj M

UTB34(b) - Part-2: ASIC Physical Design and Verification (Netlist-to-GDSII) of a Mod-N(Mod-10) Counter cover

UTB34(b) - Part-2: ASIC Physical Design and Verification (Netlist-to-GDSII) of a Mod-N(Mod-10) Counter

Dr Mamidi Nagaraju, Ashwini H

UTB34(a) - Part-1: ASIC Front-end Design and Verification (RTL-to-Netlist) of a Mod-N(Mod-10) Counter using Cadence EDA Tools cover

UTB34(a) - Part-1: ASIC Front-end Design and Verification (RTL-to-Netlist) of a Mod-N(Mod-10) Counter using Cadence EDA Tools

Dr Mamidi Nagaraju

UTB33(b) - Part-2: ASIC Physical Design and Implemetation of SPI Protocol (Netlist-to-GDSII) cover

UTB33(b) - Part-2: ASIC Physical Design and Implemetation of SPI Protocol (Netlist-to-GDSII)

Dr Mamidi Nagaraju

UTB33(a) - Part 1: ASIC Design and Verification of SPI Communication Protocol using Cadence EDA Tools (RTL-to-Netlist) cover

UTB33(a) - Part 1: ASIC Design and Verification of SPI Communication Protocol using Cadence EDA Tools (RTL-to-Netlist)

Dr Mamidi Nagaraju

UTB32 - Design & Implementation of 1-Bit Full Adder using Cadence Tools cover

UTB32 - Design & Implementation of 1-Bit Full Adder using Cadence Tools

Dr Mamidi Nagaraju

UTB31 (b) - Part-2: Physical Design and Verification of PWM Generator (Netlist-to-GDSII) cover

UTB31 (b) - Part-2: Physical Design and Verification of PWM Generator (Netlist-to-GDSII)

Dr Mamidi Nagaraju

UTB31 (a) - Part-1: ASIC Design and Verification of PWM Generator (RTL-to-Netlist) cover

UTB31 (a) - Part-1: ASIC Design and Verification of PWM Generator (RTL-to-Netlist)

Dr Mamidi Nagaraju, Ashwini H